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Overview of the Technology supported by our Foundry partners

Process Technology Description
BCD CMOS
  • 0.13µm, 0.18µm, 0.35µm
  • Up to 120V
  • Embedded NVM
  • 900V UHV
Analog & Mixed Signal
  • 0.18µm
  • Up to 30V
  • Low Noise Components
  • Single gate oxide
Power Discrete
  • Low Voltage / High Voltage MOSFET
  • IGBT, SiC, GaN (all in development)
eNVM
  • OTP
  • MTP
  • SRAM/ROM

Main packaging solutions being offered by our partner suppliers

Package Family Description
Wafer Level CSP
  • 1P1M
  • Bump on Pad. Low-cost solution.
  • 2P1M
  • Bump on RDL without UBM.
  • 2P2M
  • Bump on RDL with UBM. Widely used structure.
  • 3P3M
  • Dual RDL.
Copper Pillar Bump
  • 1M
  • Bump on pad without re-passivation
  • 1P1M
  • Bump on pad with re-passivation
  • 1P2M
  • Bump with RDL
  • 1P2M
  • Bump with RDL and micro via
  • 2P2M
  • Bump with RDL
BGA/LGA
  • Body size range from 3mm x 3mm up to 12mm x 12mm
  • Ball pitch of 0.4mm, 0.5mm and 0.65mm are available
  • Typical package thickness range 0.8mm to 1.4mm
  • Au or Cu wire, substrate with 2 or 4 layers, Single-die, multi-die, stacked-die.
QFN/DFN
  • Package thickness range from 0.35mm to 0.85mm
  • Body size available from 1mm x 1mm to 14mm x 14mm
  • Single-die, multi-die, stacked-die.
  • Wettable flank, Chip-on-Lead (COL), Au or Cu wire options
QFP
  • From 1mm to 3mm package thickness.
  • Body size available from 7mm x 7mm to 28mm x 28mm
  • Single-die, multi-die, stacked-die
  • Au or Cu wire options
TO, SOT, SOIC, SSOP, TSSOP
  • A wide range of different options
Flip-Chip with Copper Pillar Bump
  • Available in QFN, DFN, SOP and TSOT
High Power CSP
  • Copper pillar bump size up to 150mm x 750mm aspect ratio

Our test development services cover wafer probe and package final testing, ranging from new silicon verification, device characterization, test program optimization, conversion to other test platform and transfer from engineering activity to mass production.

The team works with 3rd party partners to provide cost-effective solutions for analog, digital, RF and mixed signal devices.

Contact us to discuss about your requirements and supported test platforms.


From device prototype to production release stage, we provide a wide range of product engineering services.

  • Manufacturing flow definition
  • Product cost analysis
  • Backend assembly BOM and Process qualification
  • Device characterization
  • Yield analysis, improvement and management
  • Product cost reduction review and execution
  • Yield Management System (YMS) using our own low-cost YMS tool

Producing a product with built-in quality and reliability is the center of our focus. The services being offered encompass NPI and initial production run. We use labs in the Bay Area and Asia for some of those services.


QMS, Certification & Audit

  • QMS solution definition and development
  • DMS solution definition and development
  • Prepare for audit and certification
  • Product certification

Quality and Reliability Control

  • On-going Reliability Monitoring
  • SYL/SBL Monitor and Maverick Lot Control
  • Change Control
  • Non-conforming Material Control
  • Manufacturing Data Monitor and Control

Product & Process Qualification

  • Qualification Test Plan definition for NPI
  • Product/Device Qualification
  • Package Qualification
  • Backend assembly process optimization and qualification

We can help you navigate through the early phase of production with low-volume production (LVP) support.

We work with our local and offshore partners to provide manufacturing operations and support to cater and satisfy your early production requirements. Our experienced team provides the following skillset.

  • Supplier Management
  • Production Planning
  • Purchasing
  • Logistics